1. Field of the Invention
This invention relates to a system in package (hereinafter abbreviated to SIP) having a testability circuit interior substrate and/or an impedance matching circuit mounted on its substrate and to a socket used in the system in package.
2. Description of the Related Art
Integration technology for semiconductor integrated circuit has considerably progressed in recent years, and a large scale integration circuit that realizes a plurality of circuit devices as one integration circuit chip, which is called SOC (System On Chip), has been put into practical use. The SOC often includes a large capacity memory and a logic circuit such as a processor operating at a high speed. In order to manufacture the SOC, an insulating layer of a material having large permittivity is formed for downsizing the memory cell is formed, and an insulating layer of a material having small permittivity for realizing the high speed operation of the logic circuit such as the processor is formed. Therefore, the SOC manufacture process is complicated, and it is difficult to improve yield of the manufacture process, thereby making it difficult to reduce the SOC manufacture cost lower than a certain level.
Accordingly, an SIP that is obtained by producing each of a plurality of circuit devices forming the SOC as an integrated circuit chip and mounting the integrated circuit chips on one package is attracting attention.
One of the advantages of the SIP is that it is possible to produce the SIP by assembling integrated circuit chips that have been produced. In this case, since the integrated circuit chips to be used are those that have been produced, they are available at low prices.
Also, in the case of producing a newly developed integrated circuit chip to be mounted on the SIP, it is possible to produce each of the memory and the logic circuit, for example, as a separate integrated circuit chip. Therefore, since it is possible to produce each of the integrated circuit chips by a minimum process step, it is possible to independently improve the yield of each of the integrated circuit chips. Consequently, even when a cost for assembling a plurality of chips as one package is taken into consideration, it is possible to produce the SIP at a low cost as compared to the production cost of the SOC in which the integrated circuit chips are integrated on a silicon chip of the identical type.
However, in an SIP (or in an SOC), there is a problem that it is difficult to perform a test on the integrated circuit chips since a signal conductor for connecting the integrated circuit chips mounted on the SIP is not connected to an external connection terminal of the SIP. For example, it is possible to perform a test on a memory integrated circuit chip when all terminal signals of the memory integrated circuit chip are controlled and observed by an external device such as a testing device. Accordingly, in the case where the terminal signals of the memory integrated circuit chip are connected only to other internal integrated circuit chips and not connected to the external connection terminal of the SIP, it is impossible to perform the test on the memory integrated circuit chip.
In recent years, a testability circuit interior substrate such as a boundary scanning circuit that is normalized by JTAG (Joint Test Action Group) is provided in some cases in an integrated circuit chip. In such case, the test on the integrated circuit chip is facilitated. However, many of those that have heretofore been on the market as a general-purpose component, particularly the memory integrated circuit chip, for example, are not provided with such testability circuit interior substrate. The integrated circuit chip to be mounted on the SIP is usually supplied as a baring die (in this specification, the baring die means an integrated circuit obtained by dicing a wafer, and the integrated circuit means the baring die that is mounted in a package). Therefore, it is necessary to develop a strategy for facilitating the test by taking the above-described reality into consideration when designing and producing an SIP.
As to the problem of difficulty in conducting the test on the SIP, Patent Document 1 described below discloses a technology for facilitating a test on an SIP by forming a circuit for assisting a test on a first integrated circuit chip (e.g. memory integrated circuit) mounted on the SIP on a second integrated circuit chip mounted on the same SIP. Also, Patent Document 2 described below discloses a technology of facilitating a test on an SIP by mounting an integrated circuit chip formed of an FPGA (Field Programmable Gate Array) in addition to integrated circuit chips to be mounted on the SIP, and forming a testability circuit interior substrate using the integrated circuit chip of FPGA.
Patent Document 1: JP-A-2004-158098 (paragraphs 0009 to 0021 and FIGS. 1 to 3)
Patent Document 2: JP-A-2005-283205 (paragraphs 0015 to 0021 and FIGS. 1 and 2)
Further, it is necessary to consider measures against reflection of signals in the integrated circuit chip terminals in such SIPs. Many of recent integrated circuit chips operate at a clock frequency that is in a GHz band. In the case where the signal reflection measure is not taken when mounting the integrated circuit chip of the high speed operation on the SIP, it is difficult to accurately perform the high speed signal transmission due to the signal reflection caused by impedance mismatching.
In the technology disclosed in Patent Document 1, in the case of performing a test on an integrated circuit chip, an auxiliary circuit for the test is added to another integrated circuit chip. Therefore, it is impossible to use any existing integrated circuit as the another integrated circuit chip. In such case, since it is necessary to produce an integrated circuit chip dedicated to the SIP, the cost advantage of SIP is impaired. Also, in the technology disclosed in Patent Document 2, since an integrated circuit chip of an extra FPGA is added to an SIP, the size and the cost of the SIP are undesirably increased.
As to the signal reflection measure in the integrated circuit chip terminal, it is possible to prevent the signal reflection by adding resistance and inductance elements for impedance matching in the vicinity of the terminal of the integrated circuit chip. However, when such technology is applied to the SIP, a space for mounting the resistance and inductance elements is required to cause a disadvantage of increasing the size of SIP.